In an apparatus which is assembled by using components, such as a Large Scale Integrated circuit (LSI), an Integrated Circuit (IC), a Package (PKG), a printed board, it is desirable that an operating voltage of the apparatus can be easily set to an optimum voltage.
A power source voltage is normally set to a standardized value which is described in specifications. In this case the voltage is set to the worst value in consideration of variation of manufacturing or change of environment. Variation in setting values of the power source voltage may be ±1% to 2% because of individual differences and environment. Since a power source standard of a common LSI/IC is −5% to +5%, the above-mentioned variation occupies 40% of the budget and is a large factor.
As one of methods for reducing the variation described above, a method for setting voltage is known, in which it is checked whether or not an apparatus can be operated in various operating patterns by using several voltages before shipment. This setting method, however, has an issue that operations need a lot of time, and the effect is limited because a voltage step needs to be increased. Further, this setting method has an issue that the voltage needs to be elevated in consideration of operational environment or aging deterioration because the above method needs to be conducted before shipment.
Therefore, there is an issue that the setting voltage needs to be raised in an apparatus, and this increases power consumption thereof.
Characteristics of a LSI, an IC, a PKG, a printed board, and the like change depending on manufacturing variation or environment. If the voltage is set before shipment, the voltage setting needs to be carried out in consideration of the worst situation of environment and a margin of aging deterioration. It is very hard to run operating patterns in environment of after shipment.
Japanese Patent Application Laid-Open No. 2013-37472 discloses a method for setting a power source voltage applied to a chip, and describes that a ratio of gate delay of the critical path to wiring delay is calculated from layout data of the chip, and the power source voltage applied to the chip is set in consideration of the ratio.
However, the method for adjusting voltage mentioned above has a following issue.
In a test in the circuit using the critical path or actual operations disclosed in Japanese Patent Application Laid-Open No. 2013-37472, only noise at a particular timing can be tested. Therefore, there is an issue that the voltage adjustment is not necessarily carried out on the basis of the test using noise with the worst value.